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www.lansdale.com page 1 of 14 issue a ml12009 ml12011 mecl pll components dual modulus prescaler legacy device: motorola mc12009, mc12011 these devices are two?odulus prescalers which will divide by 5 and 6, 8 and 9, respectively. a mecl?o?ttl translator is provided to interface directly with the motorola mc12014 counter control logic. in addition, there is a buffered clock input and mecl bias voltage source. ? ml12009 480 mhz (?/6), ml12011 550 mhz (?/9) ? mecl to mttl translator on chip ? mecl and mttl enable inputs ? 5.0 or ?.2 v operation* buffered clock input series input rc typ, 20 and 4.0 pf ? vbb reference voltage ? 310 mw (typ) * when using a 5.0 v supply, apply 5.0 v to pin 1 (v cco ), pin 6 (mttl v cc ), pin 16 (v cc ), and ground pin 8 (v ee ). when using ?.2 v supply, ground pin 1 (v cco ), pin 6 (mttl v cc ), and pin 16 (v cc ) and apply ?.2 v to pin 8 (v ee ). if the translator is not required, pin 6 may be left open to conserve dc power drain. p dip 16 = ep plastic package case 648 16 1 so 16 = -5p plastic package case 751b 16 1 cross reference/ordering information motorola p dip 16 mc12009p ml12009ep soic 16 MC12009D ml12009-5p p dip 16 mc12011p ml12011ep so 16w mc12011d ml12011-5p lansdale package note : lansdale lead free ( pb ) product, as it becomes available, will be identified by a part number prefix change from ml to mle . 1 16 15 14 13 12 11 10 9 2 3 4 5 6 7 8 (top view) v cco q q mttl v cc mttl output v ee v cc e5 mecl pin connections clock v bb e2 mecl e1 mecl e3 mecl e4 mecl ( ?) ( + ) maximum ratings characteristic symbol rating unit (ratings above which device life may be impaired) power supply voltage (v cc = 0) v ee ?.0 vdc input voltage (v cc = 0) v in 0 to v ee vdc output source current continuous surge i o 50 100 madc storage temperature range t stg ?5 to 175 c (recommended maximum ratings above which performance may be degraded) operating temperature range ml12009, ml12011 t a ?0 to 85 c dc fan?ut (note 1) (gates and flip?lops) n 70 notes: 1. ac fan?ut is limited by desired system performance.
www.lansdale.com lansdale semiconductor, inc. ml12009, ml12011 page 2 of 14 issue a 0.1 f ml12011 1.0 k 14 v bb 32 q 4 q4 15 recommended circuitry for ac coupled inputs. mttl out + 4 5 q 4 q2 c q4 d c toggle flip flop d c d c q1 q3 figure 1. logic diagrams mecl e1 mecl e2 mttl e4 mecl e3 mttl e5 mecl to mttl translator mttl out + 0.1 f 1.0 k 1000 pf ml12009 4 5 q3 2 q 3 3 14 v bb 15 recommended circuitry for ac coupled inputs. c d c d q 1 q1 c d q2 q3 q 3 9 10 11 12 13 mecl e1 mecl e2 mttl e4 mecl e3 mttl e5 9 10 11 12 13 7 7 clock input 1000 pf clock input figure 2. typical frequency synthesizer application mecl to mttl translator f ref low?ass filter f out phase detector mc4044/ml4044 ml12009 ml12011 ml12013 a programmable counter mc4016/ml4016 modulus enable line counter control logic mc12014 n p programmable counter mc4016/ml4016 counter reset line zero detect line voltage?ontrolled oscillator mc1648/ml1648 f out
www.lansdale.com page 3 of 14 issue a lansdale semiconductor, inc. ml12009, ml12011 figure 2b shows a generic block diagram of connecting a prescaler to a pll device that supports dual modulus controls. applicataion not an535 describes using a two?odulus prescaler technique. by using prescaler higher frequencies can be achieved than by a single cmos pll device. ml12009/11 figure 2b generic block diagram showing prescaler connection to pll device vco loop filter prescaler pll ml145146 ml145158 ml145159 fout fin mc mc in
www.lansdale.com page 4 of 14 issue a lansdale semiconductor, inc. ml12009, ml12011 electrical characteristics (supply voltage = ?.2 v, unless otherwise noted.) test limits pin under ?0 c 25 c 85 c characteristic symbol under test min max min max min max unit power supply drain current i cc1 8 ?8 ?0 ?0 madc i cc2 6 5.2 5.2 5.2 madc input current i inh1 15 11 12 13 375 375 375 375 250 250 250 250 250 250 250 250 adc i inh2 4 5 1.7 1.7 6.0 6.0 2.0 2.0 6.0 6.0 2.0 2.0 6.4 6.4 madc i inh3 5 0.7 3.0 1.0 3.0 1.0 3.6 i inh4 9 10 100 100 100 100 100 100 adc leakage current i inl1 15 11 12 13 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 adc i inl2 9 10 ?.6 ?.6 ?.6 ?.6 ?.6 ?.6 madc reference voltage v bb 14 ?.360 ?.160 vdc logic ??output voltage v oh1 (note 1) 2 3 ?.100 ?.100 ?.890 ?.890 ?.000 ?.000 ?.810 ?.810 ?.930 ?.930 ?.700 ?.700 vdc v oh2 7 ?.8 ?.6 ?.4 logic ??output voltage v ol1 (note 1) 2 3 ?.990 ?.990 ?.675 ?.675 ?.950 ?.950 ?.650 ?.650 ?.925 ?.925 ?.615 ?.615 vdc v ol2 7 ?.26 ?.40 ?.48 logic ??threshold voltage v oha (note 2) 2 3 ?.120 ?.120 ?.020 ?.020 ?.950 ?.950 vdc logic ??threshold voltage v ola (note 3) 2 3 ?.655 ?.655 ?.630 ?.630 ?.595 ?.595 vdc short circuit current i os 7 ?5 ?0 ?5 ?0 ?5 ?0 madc notes: 1. test outputs of the device must be tested by sequencing through the truth table. all input, power supply and ground voltages must be maintained between tests. the clock input is the waveform shown. 2. in addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. the clock input is the waveform shown. 3. in addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. the clock input is the waveform shown. each mecl 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibr ium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lin ear fpm is maintained. outputs are terminated through a 50 resistor to ?.0 v. test procedures are shown for only one gate. the other gates are tested in the same manner. v ihmax v ilmin clock input
www.lansdale.com page 5 of 14 issue a lansdale semiconductor, inc. ml12009, ml12011 electrical characteristics (continued) (supply voltage = ?.2 v, unless otherwise noted.) test voltage/current values volts @ test temperature v ihmax v ilmin v ihamin v ilamax v ih v ilh ?0 c ?.890 ?.990 ?.205 ?.500 ?.8 ?.7 25 c ?.810 ?.950 ?.105 ?.475 ?.8 ?.7 85 c ?.700 ?.925 ?.035 ?.440 ?.8 ?.7 pin under test voltage applied to pins listed below characteristic symbol u n d er test v ihmax v ilmin v ihamin v ilamax v ih v il gnd power supply drain current i cc1 8 1,16 i cc2 6 4 5 6 input current i inh1 15 11 12 13 15 11 12 13 1,16 1,16 1,16 1,16 i inh2 4 5 5 5 4 4 6 6 i inh3 5 4 5 6 i inh4 9 10 9 10 1,16 1,16 leakage current i inl1 15 11 12 13 1,16 1,16 1,16 1,16 i inl2 9 10 9 10 1,16 1,16 reference voltage v bb 14 1,16 logic ??output voltage v oh1 (note 1) 2 3 11,12,13 11,12,13 9,10 9,10 1,16 1,16 v oh2 7 5 4 6 logic ??output voltage v ol1 (note 1) 2 3 11,12,13 11,12,13 9,10 9,10 1,16 1,16 v ol2 7 4 5 6 logic ??threshold voltage v oha (note 2) 2 3 11,12,13 11,12,13 1,16 1,16 logic ??threshold voltage v ola (note 3) 2 3 11,12,13 11,12,13 1,16 1,16 short circuit current i os 7 5 4 7 6 notes: 1. test outputs of the device must be tested by sequencing through the truth table. all input, power supply and ground voltages must be maintained between tests. the clock input is the waveform shown. 2. in addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. the clock input is the waveform shown. 3. in addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. the clock input is the waveform shown. v ihmax v ilmin clock input
www.lansdale.com page 6 of 14 issue a lansdale semiconductor, inc. ml12009, ml12011 electrical characteristics (continued) (supply voltage = ?.2 v, unless otherwise noted.) test voltage/current values volts ma @ test temperature v iht v ilt v ee i l i ol i oh ?0 c ?.2 ?.4 ?.2 ?.25 16 ?.40 25 c ?.2 ?.4 ?.2 ?.25 16 ?.40 85 c ?.2 ?.4 ?.2 ?.25 16 ?.40 pin under test voltage applied to pins listed below characteristic symbol u n d er test v iht v ilt v ee i l i ol i oh gnd power supply drain current i cc1 8 8 1,16 i cc2 6 8 6 input current i inh1 15 11 12 13 9,10 9,10 9,10 8 8 8 8 1,16 1,16 1,16 1,16 i inh2 4 5 8 8 6 6 i inh3 5 8 6 i inh4 9 10 8 8 1,16 1,16 leakage current i inl1 15 11 12 13 8,15 8,11 8,12 8,13 1,16 1,16 1,16 1,16 i inl2 9 10 8 8 1,16 1,16 reference voltage v bb 14 8 14 1,16 logic ??output voltage v oh1 (note 1) 2 3 8 8 1,16 1,16 v oh2 7 8 7 6 logic ??output voltage v ol1 (note 1) 2 3 8 8 1,16 1,16 v ol2 7 8 7 6 logic ??threshold voltage v oha (note 2) 2 3 9,10 9,10 8 8 1,16 1,16 logic ??threshold voltage v ola (note 2) 2 3 9,10 9,10 8 8 1,16 1,16 short circuit current i os 7 8 6 notes: 1. test outputs of the device must be tested by sequencing through the truth table. all input, power supply and ground voltages must be maintained between tests. the clock input is the waveform shown. 2. in addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. the clock input is the waveform shown. 3. in addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. the clock input is the waveform shown. v ihmax v ilmin clock input
www.lansdale.com page 7 of 14 issue a lansdale semiconductor, inc. ml12009, ml12011 electrical characteristics (supply voltage = 5.0 v, unless otherwise noted.) test limits pin under ?0 c 25 c 85 c characteristic symbol under test min max min max min max unit power supply drain current i cc1 8 ?8 ?0 ?0 madc i cc2 6 5.2 5.2 5.2 madc input current i inh1 15 11 12 13 375 375 375 375 250 250 250 250 250 250 250 250 adc i inh2 4 5 1.7 1.7 6.0 6.0 2.0 2.0 6.0 6.0 2.0 2.0 6.4 6.4 madc i inh3 5 0.7 3.0 1.0 3.0 1.0 3.6 i inh4 9 10 100 100 100 100 100 100 adc leakage current i inl1 15 11 12 13 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 adc i inl2 9 10 ?.6 ?.6 ?.6 ?.6 ?.6 ?.6 madc reference voltage v bb 14 3.67 3.87 vdc logic ??output voltage v oh1 (note 1) 2 3 3.900 3.900 4.110 4.110 4.000 4.000 4.190 4.190 4.070 4.070 4.300 4.300 vdc v oh2 7 2.4 2.6 2.8 logic ??output voltage v ol1 (note 1) 2 3 3.070 3.070 3.385 3.385 3.110 3.110 3.410 3.410 3.135 3.135 3.445 3.445 vdc v ol2 7 0.94 0.80 0.72 logic ??threshold voltage v oha (note 2) 2 3 3.880 3.880 3.980 3.980 4.050 4.050 vdc logic ??threshold voltage v ola (note 3) 2 3 3.405 3.405 3.430 3.430 3.465 3.465 vdc short circuit current i os 7 ?5 ?0 ?5 ?0 ?5 ?0 madc notes: 1. test outputs of the device must be tested by sequencing through the truth table. all input, power supply and ground voltages must be maintained between tests. the clock input is the waveform shown. 2. in addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. the clock input is the waveform shown. 3. in addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. the clock input is the waveform shown. each mecl 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibr ium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lin ear fpm is maintained. outputs are terminated through a 50 resistor to ?.0 v. test procedures are shown for only one gate. the other gates are tested in the same manner. v ihmax v ilmin clock input
www.lansdale.com page 8 of 14 issue a lansdale semiconductor, inc. ml12009, ml12011 electrical characteristics (continued) (supply voltage = 5.0 v, unless otherwise noted.) test voltage/current values volts @ test temperature v ihmax v ilmin v ihamin v ilamax v ih v ilh ?0 c 4.110 3.070 3.795 3.500 2.4 0.5 25 c 4.190 3.110 3.895 3.525 2.4 0.5 85 c 4.300 3.135 3.965 3.560 2.4 0.5 pin under test voltage applied to pins listed below (v ) characteristic symbol u n d er test v ihmax v ilmin v ihamin v ilamax v ih v il (v ee ) gnd power supply drain current i cc1 8 8 i cc2 6 4 5 8 input current i inh1 15 11 12 13 15 11 12 13 8 8 8 8 i inh2 4 5 5 5 4 4 8 8 i inh3 5 4 5 8 i inh4 9 10 9 10 8 8 leakage current i inl1 15 11 12 13 8,15 8,11 8,12 8,13 i inl2 9 10 9 10 8 8 reference voltage v bb 14 8 logic ??output voltage v oh1 (note 1) 2 3 11,12,13 11,12,13 9,10 9,10 8 8 v oh2 7 5 4 8 logic ??output voltage v ol1 (note 1) 2 3 11,12,13 11,12,13 9,10 9,10 8 8 v ol2 7 4 5 8 logic ??threshold voltage v oha (note 2) 2 3 11,12,13 11,12,13 8 8 logic ??threshold voltage v ola (note 3) 2 3 11,12,13 11,12,13 8 8 short circuit current i os 7 5 4 7 8 notes: 1. test outputs of the device must be tested by sequencing through the truth table. all input, power supply and ground voltages must be maintained between tests. the clock input is the waveform shown. 2. in addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. the clock input is the waveform shown. 3. in addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. the clock input is the waveform shown. v ihmax v ilmin clock input
www.lansdale.com page 9 of 14 issue a lansdale semiconductor, inc. ml12009, ml12011 electrical characteristics (continued) (supply voltage = 5.0 v, unless otherwise noted.) test voltage/current values volts ma @ test temperature v iht v ilt v cc i l i ol i oh ?0 c 2.0 0.8 5.0 ?.25 16 ?.40 25 c 2.0 0.8 5.0 ?.25 16 ?.40 85 c 2.0 0.8 5.0 ?.25 16 ?.40 pin under test voltage applied to pins listed below (v ) characteristic symbol u n d er test v iht v ilt v cc i l i ol i oh (v ee ) gnd power supply drain current i cc1 8 1,16 8 i cc2 6 6 8 input current i inh1 15 11 12 13 9,10 9,10 9,10 1,16 1,16 1,16 1,16 8 8 8 8 i inh2 4 5 6 6 8 8 i inh3 5 6 8 i inh4 9 10 1,16 1,16 8 8 leakage current i inl1 15 11 12 13 1,16 1,16 1,16 1,16 8,15 8,11 8,12 8,13 i inl2 9 10 1,16 1,16 8 8 reference voltage v bb 14 1,16 14 8 logic ??output voltage v oh1 (note 1) 2 3 1,16 1,16 8 8 v oh2 7 6 7 8 logic ??output voltage v ol1 (note 1) 2 3 1,16 1,16 8 8 v ol2 7 6 7 8 logic ??threshold voltage v oha (note 2) 2 3 9,10 9,10 1,16 1,16 8 8 logic ??threshold voltage v ola (note 3) 2 3 9,10 9,10 1,16 1,16 8 8 short circuit current i os 7 6 8 notes: 1. test outputs of the device must be tested by sequencing through the truth table. all input, power supply and ground voltages must be maintained between tests. the clock input is the waveform shown. 2. in addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. the clock input is the waveform shown. 3. in addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. the clock input is the waveform shown. v ihmax v ilmin clock input
www.lansdale.com page 10 of 14 issue a lansdale semiconductor, inc. ml12009, ml12011 switching characteristics pin ml12509, ml12511, ml12513 test voltages / waveforms applied to pins listed below: pin under ?0 c 25 c 85 c pulse pulse pulse v ihmin v ilmin v f v ee v cc characteristic symbol under test min typ max min typ max min typ max unit pulse gen.1 pulse gen.2 pulse gen.3 v ihm i n v ilm i n v f ?.0 v v ee ?.0 v v cc +2.0 propagation delay (see figures 3 and 5) t 15+ 2+ t 15+ 2 t 5+ 7+ t 5 7 2 2 7 7 8.1 7.5 8.4 6.5 8.1 7.5 8.1 6.5 8.9 8 2 8.9 7.1 ns 15 15 a a 11,12,13 11,12,13 9,10 9,10 8 8 8 8 1,6,16 1,6,16 1,6,16 1,6,16 setup time (see figures 4 and 5) t setup1 t setup2 11 9 5.0 5.0 5.0 5.0 5.0 5.0 ns ns 15 15 * * * 11,12,13 9,10 * 8 8 1,6,16 1,6,16 release time (see figures 4 and 5) t rel1 t rel2 11 9 5.0 5.0 5.0 5.0 5.0 5.0 ns ns 15 15 * * * 11,12,13 9.10 * 8 8 1,6,16 1,6,16 toggle frequency (see figure 6) ml12509 : 5/6 ml12511 : 8/9 f max 2 440 500 480 550 440 500 mhz 11 11 8 8 16 16 *test inputs sequentially, with pulse generator 2 or 3 as indicated connected to input under test, and the voltage indicated ap plied to the other input(s) of the same type ( i.e., mecl or mttl). ?0 c 25 c 85 c v ihmin 1.03 1.115 1.20 vdc v ilmin 0.175 0.200 0.235 vdc figure 3. ac voltage waveforms mttl out + in q (pin 3) q (pin 2) v ilmin v ihmin ?.5 v t + t++ 20% 80% 50% 50% 50% 50% t t++ pulse generator 1 pulse generator 3 divide by 5 ml12509 divide by 8 ml12511 di id b 10 ml12513 divide by 6 ml12509 divide by 9 ml12511 di id b 11 ml12513 t setup1 t setup2 +1.5 v 50 % 50% 50% 80% 80% 80% 80% 20% 20% 20% 20% 90% 90% 10% 10% t rel2 ?.5 v v ihmin v ilmin v ihmin v ilmin 0 v v ee t rel1 50% pulse generator 1 pulse generator 2 q (pin 2) figure 4. setup and release time waveforms pulse generator 3 pulse generator 1 pulse generator 2 q (pin 2) v ihmin v ilmin v ihmin v ilmin 0 v v ee
www.lansdale.com page 11 of 14 issue a lansdale semiconductor, inc. ml12009, ml12011 figure 5. ac test circuit a ll pulse generators are eh 137 or equiv. pulse generators 1 and 2: prf = 10 mhz pw = 50% duty cycle t + = t ?= 2.0 0.2 ns pulse generator 3: prf = 2.0 mhz pw = 50% duty cycle t + = t ?= 5.0 0.5 ns all resistors are +1%. all input and output cables to the scope are equal lengths of 50 coaxial cable. the 1950 resistor at pin 7 and the scope termination impedance constitute a 40 :1 attenuator probe. c t = 15 pf = total parasitic capacitance which includes probe, wiring, and load capacitance. unused output connected to a 50 resistor to ground. v in 50 100 v in pulse generator #1 pulse generator #2 pulse generator #3 a mc10109 or equiv. (scope channel a) 50 950 v cc = 2.0 v 25 f 13 12 11 10 9 15 14 5 4 0.1 f + v ee = ?.0 v 8 mecl to mttl trans lator v bb c e5 e4 e3 e2 e1 1 6 16 0.1 f 2 3 7 v ee = ?.0 v c t 1950 v out v out (scope channel b) q q 50 100 v in 50 v in v out
www.lansdale.com page 12 of 14 issue a lansdale semiconductor, inc. ml12009, ml12011 figure 6. maximum frequency test circuit divide by 6 800 mv clock input q (pin 2) 3 cycles 3 cycles 850 mv typ divide by 9 800 mv 850 mv typ 5 cycles 4 cycles clock input q (pin 2) 1.0 k (to scope) v in v ee 0.1 f 0.1 f 0.1 f 0.1 f 5.0 f 13 12 11 10 9 15 14 v ee = ?.0 v 8 v bb c e5 e4 e3 e2 e1 1 16 v cc = 2.0 v v out to scope 2 3 q q unused output connected to a 50 resistor to ground
www.lansdale.com page 13 of 14 issue a lansdale semiconductor, inc. ml12009, ml12011 enable = 0 enable = 1 enable = 1 enable = 0 111 011 001 010 101 110 100 000 0101 0010 1000 1100 1010 1110 0110 0000 0111 1111 0001 1101 1001 0011 1011 0100 figure 7. state diagram divide by 8/9 (ml12011) divide by 5/6 (ml12009/ml12509) enable = 1 enable = 1 q1 q2 q3 1 1 1 0 1 1 0 0 1 0 0 0 1 0 0 1 1 0 q1 q2 q3 q4 1 1 1 1 0 1 1 1 0 0 1 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 0 0 0 1 1 0 0 applications information the primary application of these devices is as a high?peed variable modulus prescaler in the divide by n section of a phase?ocked loop synthesizer used as the local oscillator of two?ay radios. proper vhf termination techniques should be followed when the clock is separated from the prescaler by any appreciable distance. in their basic form, these devices will divide by 5/6 or 8/9. division by 5, or 8 occurs when any one or all of the five gate inputs e1 through e5 are high. division by 6, or 9 occurs when all inputs e1 through e5 are low. (unconnected mttl inputs are normally high, unconnected mecl inputs are normally low). with the addition of extra parts, many different division configurations may be obtained.
www.lansdale.com page 14 of 14 issue a lansdale semiconductor, inc. ml12009, ml12011 so 16 = -5p plastic package (ml12009-5p, ml12011-5p) case 751b?5 (so?6) issue j outline dimensions p dip 16 = ep plastic package (ml12009ep, ml12011ep) case 648?8 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ? b f c s h g d j l m 16 pl seating 18 9 16 k plane ? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? ? m 0.25 (0.010) b s ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 lansdale s emiconductor reserves the right to make changes without further notice to any products herein to improve reliabili- ty, function or design. lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. ?ypical parameters which may be provided in lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. all operating parameters, including ?ypicals must be validated for each customer application by the customers technical experts. lansdale s emiconductor is a registered trademark of lansdale s emiconductor, inc.

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